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pdm digital input, mono 2. 7 w class - d audio amplifier data sheet SSM2537 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features filterless digital class - d amplifier pulse density modulation (pdm) digital input interface 2. 7 w into 4 load and 1.4 w into 8 load at 5.0 v supply with <1% total harmonic distortion plus noise (thd + n) available in 9 - ball, 1.2 mm 1.2 mm, 0.4 mm pitch wlcsp 93% efficiency into 8 at full scale output noise: 25 v rms at 3.6 v, a - weighted thd + n: 0.005% at 1 khz, 100 mw output power ps r r: 8 0 db at 217 hz, with dither in put quiescent power consumption: 5.1 mw (vdd = 1.8 v, pvdd = 3.6 v, 8 + 33 h load) pop - and - click suppression configurable with pdm pattern inputs short - circuit and thermal protection with autorecovery smart power - down when pdm stop condition or no clo ck input detected 64 f s or 128 f s operation supporting 3 mhz and 6 mhz clocks dc blocking high - pass filter and static input dc protection user - selectable ultralow emi emissions and low latency modes power - on reset (por) minimal external passive components applications mobile handsets general description the SSM2537 is a pdm digital input class - d power amplifier that offers higher performance than existing dac plus class - d solutions. the SSM2537 is ideal for power sensitive applications where system noise can corrupt the small analog signal sent to the amplifier, such as mobile phones and portable media players. the SSM2537 combines an audio digital - to - analog converter (dac), a power amplifier, and a pdm digital interface on a single chip. the integrated dac plus analog sigma - delta ( - ) modulator architecture enables extremely low real - world power consumption from digital audio sources with excellent audio performance. using the SSM2537 , audio can be transmitted digitally to the audio amplifier, signifi cantly reducing the effect of noise sources such as gsm interference or other digital signals on the transmitted audio. the SSM2537 is capable of delivering 2. 7 w of continu - ous output power with <1% thd + n d riving a 4 ? load from a 5.0 v supply. the SSM2537 features a high efficiency, low noise modulation scheme that requires no external lc output filters. the closed - loop, three - level modulator design retains the benefits of an all - digital amplifier, yet enables very good psrr and audio performance. the modulation continues to provide high efficiency even at low output power and has an snr of 102 db pdm input. spread - spectrum pulse density modulation is used to pro vide lower emi - radiated emissions compared with other class - d architectures. the SSM2537 has a four - state gain and sample frequency selection pin that can select two different gain settings, optimized for 3.6 v and 5 v operation. this same pin controls the internal digital fil - tering and clocking, which can be set for a 64 f s or 128 f s input sample rate to support both 3 mhz and 6 mhz pdm clock rates. the SSM2537 has a micropower shutdown mode with a typical sh utdown current of 1 .6 a for both power supplies. shutdown is enabled automatically by gating input clock and data signals. a standby mode can be entered by applying a designated pdm stop condition sequence. the device also includes pop - and - click sup - pression circuitry. this suppression circuitry minimizes voltage glitches at the output when entering or leaving the low power state, reducing audible noises on activation and deactivation. the SSM2537 is specified over the industrial temperature range of ?40 c to +85 c. it has built - in thermal shutdown and output short - circuit protection. it is available in a 9 - ball, 1. 2 mm 1. 2 mm wafer level chip scale package (wlc sp). functional block dia gram figure 1. pdat vdd power-on reset clocking power control pclk gain_fs lrsel out+ out? pvdd pgnd input interface filtering/ dac - class-d modulator full-bridge power stage SSM2537 10981-001
SSM2537 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 digital input/output specifications ........................................... 4 pdm interface digital timing specifications .......................... 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 13 master clock ............................................................................... 13 power supplies ............................................................................ 13 power control ............................................................................. 13 power - on reset/voltage supervisor ....................................... 13 system gain/input frequency .................................................. 13 pdm pattern control ................................................................ 14 emi noise .................................................................................... 14 pdm channel selection ............................................................ 14 output modulation description .............................................. 14 applications information .............................................................. 15 layout .......................................................................................... 15 power supply decoupling ......................................................... 15 outline dimensions ....................................................................... 16 ordering g uide .......................................................................... 16 revision history 10 /12 revision 0: initial version
data sheet SSM2537 rev. 0 | page 3 of 16 specifications pvdd = 5.0 v, vdd = 1.8 v, f s = 128, t a = 25c, r l = 8 ? + 33 h, unless otherwise no ted. when f s = 128 , pdm clock = 6.144 mhz; when f s = 64, pdm clock = 3.072 mhz. table 1 . parameter symbol test conditions/comments min typ max unit device characteristics output power p o f = 1 khz, bw = 20 khz r l = 4 , thd = 1%, pvdd = 5.0 v 2. 7 w r l = 8 , thd = 1%, pvdd = 5.0 v 1. 4 w r l = 4 , thd = 1%, pvdd = 3.6 v 1.3 5 w r l = 8 , thd = 1%, pvdd = 3.6 v 0.7 5 w r l = 4 , thd = 1%, pvdd = 2.5 v 0.62 w r l = 8 , thd = 1%, pvdd = 2.5 v 0.35 w r l = 4 , thd = 10%, pvdd = 5.0 v 3.38 w r l = 8 , thd = 10%, pvdd = 5.0 v 1.8 w r l = 4 , thd = 10%, pvdd = 3.6 v 1.7 w r l = 8 , thd = 10%, pvdd = 3.6 v 0. 9 3 w r l = 4 , thd = 10%, pvdd = 2.5 v 0.78 w r l = 8 , thd = 10%, pvdd = 2.5 v 0.44 w total harmonic distortion plus noise thd + n f = 1 khz p o = 100 mw into 8 , pvdd = 3.6 v 0. 005 % p o = 500 mw into 8 , pvdd = 3.6 v 0. 0 15 % p o = 1 w into 8 , pvdd = 5.0 v 0. 0 2 % efficiency p o = 2 w into 4 , pvdd = 5.0 v 88 % p o = 1.4 w into 8 , pvdd = 5.0 v 93 % average switching frequency f sw no input 290 khz closed - loop gain gain ?6 dbfs pdm input, btl output, f = 1 khz gain = 3.6 v 3.5 v p gain = 5.0 v 4.78 v p differential output offset voltage v oos gain = 3.6 v 0.5 mv low power mode wake time t wake 0.5 ms input sampling frequency f s f s = 64 1.84 3.072 3.23 mhz f s = 128 3.68 6.144 6.46 mhz propagation delay t pd f s = 6.144 mhz, normal operation 35 s f s = 6.144 mhz, low latency operation 15 s power supply supply voltage range amplifier power supply pvdd 2.5 3.6 5.5 v digital power supply vdd 1.65 1.8 1.95 v power supply rejection ratio psrr v ripple = 100 mv at 100 hz 80 db v ripple = 100 mv at 1 khz 80 db v ripple = 100 mv at 10 khz 7 5 db supply current, h - bridge i pvdd dither input, 8 + 33 h load pvdd = 5.0 v, f s = 64 1.4 ma pvdd = 5.0 v, f s = 128 1.4 ma pvdd = 3.6 v, f s = 64 1. 1 ma pvdd = 3.6 v, f s = 128 1. 2 ma pvdd = 2.5 v, f s = 64 1. 0 ma pvdd = 2.5 v, f s = 128 1. 1 ma standby current pvdd = 5.0 v 2.5 a power - down current 100 na
SSM2537 data sheet rev. 0 | page 4 of 16 parameter symbol test conditions/comments min typ max unit supply current , modulator i vdd dither input, 8 + 33 h load vdd = 1.8 v, f s = 64 0.3 ma vdd = 1.8 v, f s = 128 0.6 ma standby current vdd = 1.8 v, f s = 64 37 a vdd = 1.8 v, f s = 128 68 a shutdown current vdd = 1.8 v 1.6 a noise performance output voltage noise e n dither input, a - weighted pvdd = 3.6 v, f s = 64 25 v pvdd = 3.6 v, f s = 128 27 v pvdd = 5.0 v, f s = 64 33 v pvdd = 5.0 v, f s = 128 30 v signal - to - noise ratio snr p o = 1.4 w, pvdd = 5.0 v, r l = 8 , a - weighted f s = 64 102 db f s = 128 102 db digital input/output specifications table 2 . parameter symbol min typ max unit input specifications input voltage high v ih pclk, pdat, lrsel pins 0.7 vdd 3.6 v input voltage low v il v pclk, pdat, lrsel pins ?0.3 0.3 vdd v input leakage current high i ih pdat, lrsel pins 1 a pclk pin 3 a input leakage current low i il pdat, lrsel pins 1 a pclk pin 3 a input capacitance 5 pf
data sheet SSM2537 rev. 0 | page 5 of 16 pdm interface digita l timing specificati ons table 3 . parameter limit unit description t min t max t cf 10 ns clock fall time t cr 10 ns clock rise time t ds 10 ns data setup time t dh 7 7 ns data hold time timing diagram igr pd nra timing pclk pda t left data right data t dh t ds left data right data 10981-002
SSM2537 data sheet rev. 0 | page 6 of 16 absolute maximum ratings absolute maximum ratings apply at 25c, unless otherwise noted. table 4. parameter rating pvdd supply voltage ?0.3 v to +6 v vdd supply voltage ?0.3 v to +2 v input voltage (signal source) ?0.3 v to +2 v esd susceptibility 4 kv out? and out+ pins 8 kv storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance junction-to-air thermal resistance ( ja ) is specified for the worst- case conditions, that is, a device soldered in a printed circuit board (pcb) for surface-mount packages. ja is determined according to jedec jesd51-9 on a 4-layer pcb with natural convection cooling. table 5. thermal resistance package type pcb ja unit 9-ball, 1.2 mm 1.2 mm wlcsp 2s0p 88 c/w esd caution
data sheet SSM2537 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic function description a1 pdat input pdm data signal. a2 lrsel input left/right channel select. tie to ground for left channel; pull up to vdd for right channel. a3 out? output inverting output. b1 vdd supply digital power, 1.8 v. b2 pvdd supply amplifier power, 2.5 v to 5.5 v. b3 pgnd ground amplifier ground. c1 pclk input pdm interface master clock. c2 gain_fs input gain and sample rate selection pin. (connect to pvdd for typical operation.) c3 out+ output noninverting output. top view (ball side down) not to scale ball a 1 corner a 3 2 1 b c pdat out? lrsel vdd pvdd pgnd pclk gain_fs out+ 10981-003
SSM2537 data sheet rev. 0 | page 8 of 16 typical performance characteristics figure 4. thd + n vs. output power into 8 ?, gain = 5 v, f s = 64 figure 5. thd + n vs. output power into 8 ?, gain = 5 v, f s = 128 figure 6. thd + n vs. output power into 4 ?, gain = 5 v, f s = 64 figure 7. thd + n vs. output power into 4 ?, gain = 5 v, f s = 128 figure 8. thd + n vs. frequency, pvdd = 5 v, r l = 8 ?, f s = 64 figure 9. thd + n vs. frequency, pvdd = 3.6 v, r l = 8 ?, f s = 64 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) r l = 8? + 33h f s = 64 pvdd = 2.5v pvdd = 3.6v pvdd = 5v 10981-007 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) r l = 8? + 33h f s = 128 pvdd = 2.5v pvdd = 3.6v pvdd = 5v 10981-008 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) pvdd = 2.5v pvdd = 3.6v pvdd = 5v r l = 4? + 15h f s = 64 10981-009 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) pvdd = 2.5v pvdd = 3.6v pvdd = 5v r l = 4? + 15h f s = 128 10981-010 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 8? + 33h pvdd = 5v f s = 64 1w 0.25w 0.5w 10981-012 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) 0.25w 0.5w r l = 8? + 33h pvdd = 3.6v f s = 64 0.125w 10981-0 1 1
data sheet SSM2537 rev. 0 | page 9 of 16 figure 10 . thd + n vs. frequency, pvdd = 2.5 v, r l = 8 ?, f s = 64 figure 11 . thd + n vs. frequency, pvdd = 5 v, r l = 4 ?, f s = 64 figure 12 . thd + n vs. frequency, pvdd = 3.6 v, r l = 4 ?, f s = 64 figure 13 . thd + n vs. frequency, pvdd = 2.5 v, r l = 4 ?, f s = 64 figure 14 . thd + n vs. frequency, pvdd = 5 v, r l = 8 ?, f s = 128 figure 15 . thd + n vs. frequency, pvdd = 3.6 v, r l = 8 ?, f s = 128 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 8? + 33h pvdd = 2.5v f s = 64 0.25w 0.0625w 0.125w 10981-013 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 5v f s = 64 2w 0.5w 1w 10981-014 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 3.6v f s = 64 1w 0.25w 0.5w 10981-015 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 2.5v f s = 64 0.5w 0.125w 0.25w 10981-016 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 8? + 33h pvdd = 5v f s = 128 1w 0.25w 0.5w 10981-017 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 8? + 33h pvdd = 3.6v f s = 128 0.5w 0.25w 0.125w 10981-018
SSM2537 data sheet rev. 0 | page 10 of 16 figure 16 . thd + n vs. frequency, pvdd = 2.5 v, r l = 8 ?, f s = 128 figure 17 . thd + n vs. frequency, pvdd = 5 v, r l = 4 ?, f s = 128 figure 18 . thd + n vs. frequency, pvdd = 3.6 v, r l = 4 ?, f s = 128 figure 19 . thd + n vs. frequency, pvdd = 2.5 v, r l = 4 ?, f s = 128 figure 20 . quiescent current vs. supply voltage, f s = 64 figure 21 . quiescent current vs. supply voltage, f s = 128 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) r l = 8? + 33h pvdd = 2.5v f s = 128 0.125w 0.25w 0.0625w 10981-019 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 5v f s = 128 2w 0.5w 1w 10981-020 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 3.6v f s = 128 0.5w 0.25w 1w 10981-021 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequency (hz) r l = 4? + 15h pvdd = 2.5v f s = 128 0.25w 0.125w 0.5w 10981-022 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply current (ma) supply voltage (v) f s = 64 4? + 15h 8? + 33h no load 10981-024 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply current (ma) supply voltage (v) f s = 128 4? + 15h 8? + 33h no load 10981- 1 18
data sheet SSM2537 rev. 0 | page 11 of 16 figure 22 . maximum output power vs. supply voltage, r l = 8 ?, f s = 64 figure 23 . maximum output power vs. supply voltage, r l = 8 ?, f s = 128 figure 24 . maximum output power vs. supply voltage, r l = 4 ?, f s = 64 figure 25 . maximum output power vs. supply voltage, r l = 4 ?, f s = 128 figure 26 . efficiency vs. output power into 8 ?, f s = 64 figure 27 . efficiency vs. output power into 8 ?, f s = 128 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) r l = 8? + 33h f s = 64 10981-025 thd = 10% thd = 1% 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) r l = 8? + 33h f s = 128 10981-026 thd = 10% thd = 1% 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) r l = 4? + 15h f s = 64 10981-027 thd = 10% thd = 1% 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) thd = 10% thd = 1% r l = 4? + 15h f s = 128 10981-028 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output power (w) r l = 8? + 33? f s = 64 pvdd = 5v pvdd = 2.5v pvdd = 3.6v 10981-023 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output power (w) pvdd = 5v pvdd = 3.6v pvdd = 2.5v r l = 8? + 33? f s = 128 10981-030
SSM2537 data sheet rev. 0 | page 12 of 16 figure 28 . efficiency vs. output power into 4 ?, f s = 64 figure 29 . efficiency vs. output power into 4 ?, f s = 128 figure 30 . output spectrum vs. frequency figure 31 . power supply rejection ratio (psrr) vs. frequency figure 32 . turn - on response 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.6 2.0 2.2 2.4 efficiency (%) output power (w) r l = 4? + 15? f s = 64 pvdd = 5v pvdd = 3.6v pvdd = 2.5v 10981-032 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.6 2.0 2.2 2.4 efficienc y (%) output power (w) pvdd = 5v pvdd = 3.6v pvdd = 2.5v r l = 4? + 15? f s = 128 10981-033 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k amplitude (dbv) frequency (hz) r l = 8? + 33h pvdd = 5v f s = 128 10981-034 frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k power supply rejection ratio (db) 10981-035 ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 voltage (v) time (ms) output pclk 10981-036
data sheet SSM2537 rev. 0 | page 13 of 16 theory of operation master clock the SSM2537 requires a clock present at the pclk input pin to operate. this clock must be fully synchronous with the incoming digital audio on the serial interface. clock frequencies must fall in to one of these ranges: 1.84 mhz to 3.23 mhz or 3.68 mhz to 6.46 mhz. power supplies the SSM2537 requ ires two power supplies: pvdd and vdd. pvdd pvdd supplies power to the full - bridge power stage of the mosfet and its associated drive, control, and protection circuitry. it also supplies power to the digital - to -analog converter (dac) and to the class-d pdm modulator. pvdd can operate from 2.5 v to 5.5 v and must be present to obtain audio output. lowering the supply voltage of pvdd results in lower maximum output power and, therefore, lower power consumption. vdd vdd provides power to the digital logic circ uitry. vdd can operate from 1.65 v to 1.95 v and must be present to obtain audio output. lowering the supply voltage of vdd results in lower power consumption but does not affect audio performance. power control on device power - up, pvdd must first be appli ed to the device, which latches in the designated gain_fs pin functionality. the SSM2537 contains a smart power - down feature. when enabled, the smart power - down feature looks at the incoming digital audio and, if it receives the pdm stop condition of at least 129 repeated 0xac bytes (1024 clock cycles), it places the SSM2537 in standby mode . in standby mode , pclk can be removed, resulting in a full power - down state. this state is the lowest power condition possible. when pclk is turned on again and a single non - stop condition input is received, the SSM2537 leaves the full power - down state and resumes normal operation under the default setting as indicated by the gain_fs pin state. power - on reset/voltage sup ervisor the SSM2537 includes an internal power - on reset and voltage super visor circuit. this circuit provides an inter nal reset to bmm circuitry when pvdd or vdd is substantially below the n ominal operating threshold. this simplifies supply sequencing during initial power - on. the circuit also monitors the power supplies to the ic. if the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. this is done to ensure that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal con dition. system gain/input fr equency the gain_fs pin is used to set the internal gain and filtering configuration for different sample rates of the SSM2537 . this pin can be set to one of four states by connectin g the pin either to pvdd or to p gnd with or without a 47 k? resistor (see table 7 ). the internal gain and filtering can also be set via pdm pattern control, allowing these settings to be modified during operation (see the pdm pattern control section). the SSM2537 has an internal analog gain control such that when gain_fs is tied to p gnd or pvdd via a 47 k? resistor (5 v gain setting), a ? 6.02 dbfs pdm input signal results in an amplifier output voltage of 5 v peak. this setting should produce optimal noise perfor mance when pvdd is 5 v. when the gain_fs pin is tied to pvdd or pulled directly to p gnd, the gain is adjusted so that a ?6.02 dbfs pdm input signal results in an amplifier output voltage of 3.6 v peak. this setting should produce optimal noise performance when pvdd is 3.6 v. the SSM2537 can handle input sample rates of 64 f s (~3 mhz) and 128 f s (~6 mhz). different internal digital filtering is used in each of these cases. selection of the sample rate is also set via the gain_fs pin (see table 7 ). because the 64 f s mode provides better performance with lower power consumption, its use is recommended. the 128 f s mode should be used only when overall system noise performance is limited by the source modulator. table 7 . gain_fs function descriptions device setting gain _fs pin configuration f s = 128 pclk, gain = 5 v pull up to pvdd with a 47 k resistor f s = 64 pclk, gain = 5 v pull down to p gnd with a 47 k resistor f s = 128 pclk, gain = 3.6 v pull up to pvdd f s = 64 pclk, gain = 3.6 v pull down to p gnd
SSM2537 data sheet rev. 0 | page 14 of 16 pdm pattern control the SSM2537 has a simple control mechanism that can set the part for low power states and control functionality. this is accomplished by sending a repeating 8-bit pattern to the device. different patterns set different functionality (see table 8). any pattern must be repeated a minimum of 129 times. the part is automatically muted when a pattern is detected so that a pattern can be set while the part is operational without a pop/click due to pattern transition. all functionality set via patterns returns to its default values after a clock-loss power-down. table 8. pdm watermarking pa ttern control descriptions pattern control description 0xd2 gain optimized for pvdd = 3.6 v operation. 0xd4 gain optimized for pvdd = 2.5 v operation. 0xd8 gain optimized for pvdd = 5 v operation. 0xe1 ultralow emi mode. 0xe2 low latency mode with pa ttern delay (~15 s latency). 0xe4 f s set to opposite value de termined by gain_fs pin. 0xaa device reset: place device into default configuration. 0x66 mute. 0xac power-down: all blocks off except for pdm interface. normal start-up time. emi noise the SSM2537 uses a proprietary modulation and spread- spectrum technology to minimize emi emissions from the device. for applications that have difficulty passing fcc class b emission tests, the SSM2537 includes a modulation select mode (ultralow emi emissions mode) that significantly reduces the radiated emissions at the class-d outputs, particu- larly above 100 mhz. this mode is enabled by activating pdm watermarking pattern 0xe1 (see table 8). pdm channel selection the SSM2537 includes a left/right input select pin, lrsel (see table 9), that determines which of the time-multiplexed input streams is routed to the amplifier. to select the left input channel, connect lrsel to pgnd. to select the right channel, connect lrsel to vdd. at any point during amplifier operation, the logic level applied to lrsel may be changed and the output will switch the input streams without audible artifacts. no muting, watermarking pattern or synchronizing are necessary to achieve a click/pop free lrsel transition. table 9. lrsel pin function descriptions device setting lrsel pin configuration right channel select vdd left channel select pgnd output modulation description the SSM2537 uses three-level, - output modulation. each output can swing from pgnd to pvdd and vice versa. ideally, when no input signal is present, the output differential voltage is 0 v because there is no need to generate a pulse. in a real-world situation, there are always noise sources present. due to this constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. a small amount of current flows into the inductive load when the differential pulse is generated. most of the time, however, the output differential voltage is 0 v, due to the analog devices, inc., three-level, - output modulation. this feature ensures that the current flowing through the inductive load is small. when the user wants to send an input signal, an output pulse (out+ and out?) is generated to follow the input voltage. the differential pulse density (vout) is increased by raising the input signal level. figure 33 depicts three-level, - output modulation with and without input stimulus. figure 33. three-level, - output modu lation with and without input stimulus output > 0v +5v 0v out+ +5v 0v out? +5v 0v vout output < 0v +5v 0v out+ +5v 0v out? 0v ?5v vout output = 0v out+ +5v 0v +5v 0v out? +5v ?5v 0v vout 10981-006
data sheet SSM2537 rev. 0 | page 15 of 16 applications information layout as output power increase s, take care to lay out pcb traces and wires properly among the amplifier, load, and power supply. a good practice is to use short, wide p cb tracks to decrease voltage drops and minimize inductance. avoid ground loops where possible to minimize common - mode current associated with separate paths to ground. ensure that track widths are at least 200 mil per inch of track length for the lowest dcr, and use 1 oz or 2 oz copper pcb traces to further reduce ir drops and inductance. a poor layout increases voltage drops, consequently affecting efficiency. use large traces for the power supply inputs and amplifier outputs to minimize losses due to p arasitic trace resistance. proper grounding help s to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. to maintain high output swing and high peak output power, the pcb traces t hat connect the output pins to the load, as well as the pcb traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. it is also recommended that a large ground plane be used for minimum impedances. in addition, good pcb layout isolates critical analog paths from sources of high interference. separate h igh frequency circuits (analog and digital) from low frequency circuits. properly designed multilayer pcbs can reduce emi emission s and increase immunity to the rf field by a factor of 10 or more, compared with double - sided boards. a multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double - sided board is often disrupted by sig nal crossover. power supply decoupl ing to ensure high efficiency, low total harmonic distortion (thd), and high psrr, proper power supply decoupling is necessary. noise transients on the power supply lines are short - duration voltage spikes. these spikes ca n contain frequency components that extend into the hundreds of megahertz. the power supply input must be decoupled with a good quality, low esl, low esr capacitor, with a minimum value of 4.7 f. this capacitor bypasses low frequency noises to the ground plane. for high frequency transient noises, use a 0.1 f capac - itor as close as possible to the pvdd and vdd pins of the device. placing the decoupling capacitors as close as possible to the SSM2537 helps to maintain efficient performance.
SSM2537 data sheet rev. 0 | page 16 of 16 outline dimensions figure 34. 9-ball wafer level chip scale package [wlcsp] (cb-9-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option SSM2537acbz-r7 ?40c to +85c 9-ball wafer level chip scale package [wlcsp] cb-9-5 SSM2537acbz-rl ?40c to +85c 9-ball wafer level chip scale package [wlcsp] cb-9-5 eval-SSM2537z evaluation board 1 z = rohs compliant part. 0 6-25-2012-a a b c 0.560 0.500 0.440 1.240 1.200 sq 1.160 12 3 bottom view (ball side up) top view (ball side down) end view 0.300 0.260 0.220 0.80 ref 0.80 ref 0.40 ref seating plane 0.230 0.200 0.170 coplanarity 0.05 ball a1 identifier ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10981-0-10/12(0)

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